The present invention is directed to video signal processing and, more particularly, to video signal processing which employs a vertical pixel signal processing block, such as a polyphase filter.
Computer arrangements, including microprocessors and digital signal processors, have been designed for a wide range of applications and have been used in virtually every industry. For a variety of reasons, many of these applications have been directed to processing video data and have demanded minimal levels of power consumption and compactness. Some applications have further demanded a high-speed computing engine that can perform effectively on a real-time or near real-time basis. Many of these video-processing applications have required a data-signal processing circuit that is capable of performing multiple functions at ever-increasing speeds.
Increasing the power and versatility of such computing engines, however, can undermine other important goals. For example, faster computing engines consume more power and circuit real estate, whereas the ideal engine minimizes both power consumption and the amount of circuitry required to implement the computing engine.
Moreover, providing versatility and high power typically exacerbates the circuit real estate problem by requiring various types of processing circuitry, each specialized and selectively activated for different processing functions. This phenomena can be appreciated when comparing, for instance, relatively-slow general-purpose processing in video applications versus specialized video-signal filter processing used for compressing and decompressing video data in real time. Because the specialized processing circuitry is typically optimized to keep up with the real-time speeds of the video data, it is often difficult to provide a single video-data processing circuit that is adequately versatile without providing seemingly excess circuitry useful only for limited applications.
As a more particular example, many video-signal processing applications employ specialized video-signal filters for vertical signal processing which uses a specialized video-data filter known as a xe2x80x9cpolyphasexe2x80x9d filter. In video-processing applications, a polyphase filter is used to resize pixels by manipulating data stored to represent the horizontal and vertical lines used to refresh the display. In such applications, expansion or up-sampling (xe2x80x9czoom-factorxe2x80x9d greater than one) is achieved by increasing the ratio of the number of output pixels to the number of input pixels; whereas, compression or down-sampling (xe2x80x9czoom-factorxe2x80x9d less than one) is achieved by decreasing the ratio of the number of output pixels to the number of input pixels.
Due to their different functions, the type of circuit used for such general purpose video signal processing is different than the type of filtering circuit used for expanding or compressing video data. For video-data expansion, a polyphase filter typically receives the data representing multiple pixels at a first pixel rate (e.g., two pixels per cycle), and processes the pixel data by circulating it through a dozen or so line buffers. The exact manner of circulation through the line buffers depends on the scaling factor. Using the many line buffers to circulate the data and effect an appropriate delay, the polyphase filter is able to output the data to a storage unit a slower pixel rate (e.g., one pixel per cycle).
During processing when the data is not being resized, the polyphase filter and its arrangement of circular line buffers is not needed. Thus, another circuit is used to present the multiple pixels at the same rate in which they are received; thus, if the multiple pixels are received at two pixels per cycle, then they are passed to the storage unit at two pixels per cycle. The storage unit for this processing mode is larger than the storage unit that receives data from the polyphase filter; using the above example two pixels per cycle pixel rate, the storage unit for this processing mode must be twice as large.
The present invention is directed to the above-mentioned goal of minimizing the amount and types of circuits required to implement these respective modes of pixel-data resizing and other types of pixel-data processing.
Various aspects of the present invention are directed to generic de-coupling of input and output rates of sampling data when line buffers are used, and in a more specific application to a reconfigurable pixel-data processing circuit in which line buffers are used for both a vertically pixel processing mode and a nonresizing processing mode.
Consistent with one specific example embodiment, the present invention is directed to a pixel-data processing circuit being adapted to resize pixel data in a first vertically processing mode and to be reconfigured to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate.
In another particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle. Using a control circuit, the pixel-data processing circuit can switch between the first operational resizing mode and the second operational nonresizing mode.
Other example embodiments of the present invention are respectively directed to various other related aspects including method, circuit, and system-based implementations of such processing.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.